The present invention relates to a memory device and, more particularly, to a dynamic random access memory operating in high speed and with small current consumption.
A semiconductor memory device is, in general, equipped with a common data bus line for transferring data read out of a selected memory cell (i.e., read data) and data to be written into a selected memory cell (i.e., write data) between an input/output buffer portion and an inner circuit portion including a memory array, a read amplifier and a write amplifier. In this circuit configuration, the inner circuit requires control signals which indicate a read mode or a write mode operation.
While the data bus line is coupled in common to the write amplifier and the read amplifier, a write-in line for transferring write data from the write amplifier to the memory array and a read-out line for transferring read data from the memory array to the read amplifier are formed independently. Since the write-in line and the read-out line are provided independently of each other, it is possible to send column selection signals more quickly and operation speed is improved. On the other hand, this type of device needs control signals for activating the write amplifier and the read amplifier independently of each other, so that a region for forming the control signal lines becomes large. Moreover, the read amplifier is required to drive the data bus line sufficiently, so that the operation speed is lowered. This will be explained in more detail with reference to FIGS. 15 and 16.
FIG. 15 shows a circuit diagram of a. prior art semiconductor memory device. This device includes a memory array 108, a data bus line pair 110 including true and complementary lines RWBS, and RWBS, an input buffer 102, an output buffer 103, a write buffer 109, a write amplifier circuit 104, a read amplifier 105, and a write mode control circuit 101. During a read mode, the read amplifier 105 is actuated by a mode signal W1 and drives the data lines RWBS, RWBS of the data bus line 110 to Send true and complementary read data signals having an amplitude as large as the potential difference between high level and low level power source lines. Before a write mode operation, the read amplifier 105 has to be deactuated by the signal W1 to prevent a collision of read data and write data on the data bus line 110. During a write mode, the write buffer 109 is activated by the low level of the signal W1 to drive the data bus line 110 according to write data from the input buffer 102, and the write amplifier 104 is actuated by a control signal W2 to transfer the write data to the memory array 108.
FIG. 16 shows a timing chart of the read and write mode operations of the prior art device. The operation in the chart starts with the state in which an row address strobe signal RAS (not shown) has moved from a high level to a low level to fetch, a row address signal so that a potential of selected word line W became high by a row decoder 108-1 and a sense amplifier 106 amplifies a potential difference between a pair of bit lines B and B in accordance with data stored in a selected memory cell 107.
First, the read mode operation will be described. In response to a column address signal at a time when an external column address strobe signal CAS (not shown) is at "High", a column selection signal YSW goes from "Low" to "High" by a column decoder 108-2. As the column selection signal YSW goes to "High" the potential difference between the bit lines D and D is transferred to a pair of read-out lines RO and RO and further to the read amplifier 105 via N-channel transistors Q.sub.N407 to Q.sub.N410. The read amplifier 105 amplifies the potential difference thus transferred and outputs true and complementary signals representative of the read data onto the data line pair 110, these signals having an amplitude as large as the potential difference between a high and a low level power source line. In the read mode, when the external signal CAS is changed to the active low level, a write-enable signal WE is held at the high level. Accordingly, the mode control circuit 101 produces an output-enable signal OE with an active high level, so that the output buffer 103 is activated to generate an output data signal D.sub.out in response to the signals on the data bus line pair 110.
Next, the write mode operation will be described in this mode, the write enable signal WE changes to the low level in synchronism with the change in the strobe signal CAS to the low level, as show in FIG. 16. Thus, the input buffer 102 is activated according to the "High" level of the signal WO to latch input data D.sub.in and output it to the write buffer 109 as write data WD.
Subsequently, the control signal W1 goes from "High" to "Low" to put the read amplifier 105 in a deactuated state in which the output terminals of the read amplifier 105 are in high impedance state. At the same time, the write buffer 109 is actuated to drive the data bus line pair 110 in accordance with the write data WD from the input buffer 102. The control signal W2 is then changed to the high level to activate the write amplifier circuit 44 which thereby generates a high level control signal WSW and supplies a pair of write-in lines WI and W1 with true and complementary signals indicative of the write data. The high level control signal WSW turns N-channel transistors Q.sub.N403 and Q.sub.N404 ON, so that the true and complementary signals of the write data are transferred to the bit line pair D/D. The data is thus written in the selected memory cell 107
The control signal W1 is a one-shot signal having a "Low" state only during the write mode and goes to "High" when or Just before the write data is safely transferred to a memory cell 107. Subsequently, the control signal W2 and WSW goes to "Low" and the write mode operation is finished.
As apparent from the above description, since the read amplifier 105 is required to drive the data bus line pair 101 with the true and complementary read data signals having an amplitude as large as the difference between high and low level power source lines, so that the current consumption becomes large and data read-out speed is decreased. In addition, the read amplifier 105 needs a large capability for driving the data bus line pair 110 and occupies a large area. Moreover, considering a multibit construction such as a 4-bit or 8-bit, a plurality of read amplifiers and write amplifiers are provided, and therefore, the control signal lines for W1 and W2 are required to be prolonged. The occupying area for forming the control signal lines is thereby made large, and stray capacitance is also increased. Furthermore, the write amplifier 104 is activated alter deactivating the read amplifier 105 in the data write mode, and for this reason the data write operation speed is also lowered.